Any for profit SDRAM producer would know that quality of the SDRAM product is a key factor in determining the profit. Therefore, a majority of the IC producers have invested money in reducing the number of defective product, including incentives for workers, technicians and engineers to find ways to enhance the quality of the IC product. After analyzing the production volume of the IC producers for the past 25 years, a 1991 publication in the form of VISL dissertation stated that an IC producer generally invests at least 600 to 700 million dollars to increase the qualification rate to at least 85 percent. Moreover according to a 1991 publication by the Semiconductor Industry Union entitled the “International Technology Roadmap for Semiconductors in Defect Reduction”, it is stated that the qualification rate is limited to between 85 to 95 percent for the IC producer regardless of the debasing deficiency generated by the product-processing or the equipments, as shown in FIG. 1.
To reduce the waste cost of the 5 to 15 percent defective product, SDRAM producers generally undertake a repair program to mend or repair the 5 to 15 percent defective product, so as to raise the qualification rate. A few of the common repair methods adopted by the SDRAM producer are discussed hereinbelow:
(1) Logical Method
As shown in FIG. 2, the various features of this method include the testing step and patch step. The testing-step is to test whether the memory 100 has defective cells 110, and if it has, record the address of the defective cells 110. The patch step is to use comparator 120 to compare the recorded defective address 130 in the testing-step with the address of access date transferred by the CPU, and if the address of access date is in the record, it will re-map the address to the patch-memory 140 (usually SRAM). By using one of the cells in patch-memory to replace the defective cell in the testing-memory, it would cure the defective product. However, the shortcomings of this repair method are:
1. The address signal, which is transferred by the CPU, is not only presented to the testing-memory 110, but also to the patch-memory 140. So this address signal must have enough fan-out power or it can be mistakenly distinguished.
2. Since the repair process is slow the comparator 120 must compare the address one by one, and it can take a long time to patch the memory page.
3. There must be a colossal scale and high ability comparator 120, which is very expensive.
(2) Spare Fault-Tolerant Method
As shown in FIG. 3, the main feature is the repair process of the wafer test. Memory 200 will make spare array elements 220 while making the wafer. During the test, CPU sends the row address 230 to the cell of memory 200 first, then send the column address to test every memory cell after a proper TRCD. Once finding the defective cells 210, it replaces the defective cells 210 with spare array elements 220 in a radiate mode to make the defective product effective. The shortcomings of this repair method are:
1. The repair only occurs during the wafer test. If the wafer is cut or sealed, the method would fail.
2. It takes 1.5 seconds to repair every die, which is too long.
3. It increases the cost of repair in the radiate mode.
The above-described conventional repair methods, especially the latter one, greatly increase the investment cost for the SDRAM producer.